Permutation addressing system

ABSTRACT

A permutation addressing system in which up to N factorial remote stations can be addressed by a central station over only N-lines. A remote station is addressed by sequentially pulsing the N-lines in a predetermined order. After a remote station is addressed, a signal is maintained on the last line in the sequence to enable data transfer between the addressed station and the central station on the remainder of the N-lines.

United States Patent [1 1 Oliver [451 Sept. 2, 1975 PERMUTATION ADDRESSING SYSTEM [75] Inventor: Theodore A. Oliver, Ann Arbor,

Mich.

[73] Assignee: Reliance Electric Company, Toledo,

Ohio

[22] Filed: Oct. 4, 1973 [21] Appl. No.: 403,515

[52] US. Cl. .1 340/19; 187/29 AT; 340/20; 340/147 LP; 340/147 R [51] Int. Cl B66b 1/18; B66b 3/00 [58] Field of Search 340/19, 20, 21, 178, 147 LP, 340/147 R, 167 R; 187/29 R, 29 AT, 29 A], 29 Y; 178/69 G; 328/75, 69; 307/221 [56] References Cited UNITED STATES PATENTS 3,465,290 9/1969 Mitchell 340/147 R 3,495,218 2/1970 Deeg 340/167 R 3,510,586 5/1970 Wright 340/147 R 3,522,588 8/1970 Clarke et a1. 340/147 R 3,577,187 5/1971 Benson .1 340/167 R 3,634,826 l/l972 Biedermann. 340/167 R 3,701,101 10/1972 l-leiz ct al 340/163 3,728,680 4/1973 Upshur 340/147 R 3,740,709 6/1973 Savino 340/21 3,782,504 1/1974 Billmaier et a1 340/19 R Primary Examiner-lohn W. Caldwell Assistant Examiner-Donnie L. Crosland 5 7 ABSTRACT A permutation addressing system in which up to N factorial remote stations can be addressed by a central station over only N-lines. A remote station is addressed by sequentially pulsing the N-lines in a predetermined order. After a remote station is addressed, a signal is maintained on the last line in the sequence to enable data transfer between the addressed station and the central station on the remainder of the N- lines.

8 Claims, 4 Drawing Figures STATION '1 \Z STATION 2 STATION i.

| INTERFACE CONTROL I ELEVATOR r I (ADDRESS: 13,14,

PATEIIIEDSEP zIsIs SHEET 1 [IF 3 STATION 1 STATION 2 I5--\ STATION L 2 (ADDRESS: I3, I4,

I INTERFACE P L $16 1 I8 I ELEVATOR I cONTROL I I I I I I I I I I I I l LINE I3 I I I I I O I I I I I l I I I I I LINE I4 I I I I o I I I I I I I I I I I I l LINE I5 I I I I I I I I I I l I I I' 1G. 2 LINEI6 I I I I o I I I I I I I I I I I l I I I I LINE I7 I I I I I I I I I I I 2 3 4 "5 6 PATENTED 35F 2 975 ADDRESS SHIFT 3-BIT BINARY REGISTER 36 BBIT 2 31w TO 58w 5 LINE DECODER Q as Zl DATA DATA CLEAR OUT E NAB LE ADDRE s 5 DECODER ENABLE DATA D gA P ROCESSO R ADDRESS PERMUTATION ADDRESSING SYSTEM BACKGROUND OF THE INVENTION This invention relates to a communication system and more particularly to a permutation addressing system in which data is transferred over N-lines between a central station and a predetermined one of up to N factorial stations.

In systems in which data is transferred between a central station and a large number of remote stations, there is often a problem in providing a sufficient number of data lines interconnecting the stations. An elevator system in a multistory building is exemplary of one system in which this problem sometimes occurs. If we assume, for example, that the elevator system is in a -story building, there would be a remote station on each floor and remote stations on the elevator car which are connected to a centrally located elevator control. In a typical system of this type, it is necessary to have four data lines interconnected between the remote station on each floor and the elevator control. Two data lines are connected to notify the elevator control whenever either an up car or a down car button is pushed. The two additional data lines are provided for illuminating the appropriate up lamp or down lamp at the remote station when an up or a down elevator car, respectively, is requested. Thus, a system of this type may require as many as eighty wires interconnecting the four remote stations or each floor with the central elevator control.

In addition, the elevator car may be considered as one or more remote stations. The elevator car is provided with 20 push buttons to permit passengers to request the car to stop at predetermined floors. When any of the buttons in the elevator car are pushed, a signal is sent to the elevator control over a line. The elevator control may then verify that a button has been pushed by sending a signal over another line to cause the pushed button to become illuminated. To provide necessary communication between the elevator and the elevator control, it is necessary to have as many as 40 or more conductors connecting the car to the elevator control for a 20-story building. Of course, these conductors must follow the elevator as it moves up and down in the elevator shaft. The movement of the car flexes the wires which may eventually result in a fatigue failure of the wire.

A different type of system in which problems occur in transferring data or communicating between a central station and a plurality of remote stations is an integrated circuit read only memory (ROM). Due to space limitations in the package for the ROM, there are a limited-number of terminals. These terminals may be arranged in or internally connected in a matrix for ad dressing specific stations or memory locations. The problem results from the fact that integrated circuit technology presently permits a far greater number of memory locations than can be used due to the limitations in the package size which limits the number of terminals connected to the integrated circuit.

SUMMARY OF THE INVENTION According to the present invention, a permutation addressing system has been developed which permits communication between a central station and up to N factorial remote stations over only N lines or terminals. In an elevator system, for example, only five wires or lines are needed for communicating between a centrally located elevator control and separate stations. After a particular station is addressed, either an additional set of lines or, preferably, four of the five address lines may be used for transferring data between the addressed station and the elevator control while the fifth line is used to maintain the connection between the addressed station and the elevator control. Or, in an example of the invention, only eight terminals are necessary for addressing eight factorial or 40,320 individual memory locations in a digital memory such as an integrated circuit ROM.

The address for each remote station consists of a predetermined sequence in which the N data lines are pulsed. In order to establish communication with a remote station, the address of the station is stored in a shift register in an interface connecting the elevator control to the data lines. The data lines are sequentially pulsed as the address is shifted from the shift register. The pulse is then maintained on the last line in a sequence for locking the addressed remote station to the data lines. When ,data transmission is completed, the last line is released at the interface to in turn release the addressed station.

An address decoder is provided at each station. The decoder is provided with N-stages which must be set in the proper sequence. After the N-lines are pulsed in the proper sequence to set the N-stages, a clock signal is generated in the decoder to enable data transfer between the addressed station and the elevator control. The clock signal is maintained as long as a pulse or signal appears on the last line in the sequence. When this pulse is terminated, the clock signal ceases and the decoders at each of the N-stations are reset to receive a new address.

Accordingly, it is a preferred object of the invention to provide an improved system for communicating between a central station and a plurality of remote stations.

Another object of the invention is to provide a system in which data can be transferred between a central station and any one of N factorial remote stations over N- lines or terminals.

Still another object of the invention is to provide an improved system for selectively addressing remote stations over a plurality of lines wherein each remote station is identical and the address for each remote station is determined merely by the permutation in which the lines are connected to such station.

Other objects and advantages of the invention will become apparent from the following detailed description, with reference being made to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of an elevator system showing a centrally located elevator control connected to a plurality of remote stations over five lines;

FIG. 2 is a graph showing a sequence in which the lines interconnecting the elevator control and the remote stations may be pulsed for forming the unique address of one of the remote stations;

FIG. 3 is a schematic logic diagram showing an interface for connecting the elevator control to the five data lines; and

FIG. 4 is a schematic logic diagram of a typical addressed decoder for a remote station.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Turning now to the drawings and particularly to FIG. 1, the box diagram generally shows a system for providing communication between a central station 1 1 and a plurality of remote stations 12. In the following description, the system 10 will be described as being embodied in an elevator system for a multi-story building. The central station 11 includes a centrally located con trol for operating one or more elevator cars while at least some of the remote stations 12 will consist of the up and down call buttons located on each floor of the building and associated indicator lights. Five separate lines 13-17 are provided for interconnecting the central station 11 with up to 120 remote stations 12. However, it will be appreciated that additional or fewer lines may be used for greater or lesser numbers for remote stations 12. If N-lines are provided, up to N factorial stations may be connected to the central station 1 1. Thus, if the number of lines is increased from five to six, the number of remote stations may be increased from 120 to 720. Also, increasing the number of lines interconnecting the remote stations 12 and the central station 11 increases the number of data lines available for transferring information between each of the remote stations 12 and the central station 11.

The central station 11 generally comprises an elevator control 18 and an interface 19 for connecting the control 18 to the lines 13-17. The elevator control 18 may be of any conventional design, but is preferably computerized for providing fully automated operation of the elevator cars. During such automatic operation, the elevator control 18 periodically scans each of the remote stations 12 for transferring data to and from such remote stations. Scanning of a particular station 12' is initiated by the elevator control 18 supplying an address for such station 12 to the interface 19. The interface 19 then applies signals on the five lines 13-17 in a predetermined sequence for addressing the station 12'. The station 12' may, for example, have a unique address consisting of pulsing the lines 13-17 in the sequence of line 13, line 14, line 17, line 15, and finally line 16. when the last line 16 in the sequence is pulsed, a signal is maintained on this line 16 as long as communication is desirable between the station 12' and the elevator control '18. Removal of the signal from the last line 16 clears an address decoder within the addressed station 12' to permit the central station 11 to address or scan a different one of the stations of the remote stations 12.

The sequence in which the central station 11 applies signals on the lines 13-17 is shown more clearly in the graph of FIG. 2. Normally, all of the lines 13-17 are maintained at a high or logic one state. When the interface 19 at the central station 11 applies a pulse or signal on one of the lines 13-17, the line is switched to a low or logic zero state. Of course, it will be readily apparent that the logic states of the lines 13-17 may be reversed. In addressing the station 12, the interface 19 will initially switch the line 13 to a logic zero at time At a later time 1 the line 14 is switched to a logic zero. It is only necessary that the line 13 be maintained at a logic zero until the line 14 has been pulsed, although it is shown as being maintained at a zero level. At time line 17, the next line in the sequence, is pulsed. Finally, at time t,, line is pulsed, and at time t line 16 is pulsed. Line 16 will then be maintained at a low or logic zero state until time 1 During the time interval between 1;, and t data is transferred between the central station 11 and the remote station 12 over the lines 13, 14, 15 and 17. After the data transferral is completed, line 16 is returned to its normally high state at time to release the remote station 12' from the lines 13-17.

Up to five factorial addresses for different remote stations 12 may be applied over the five lines 13-17. This will be readily apparent from the fact that any one of the five lines 13-17 may be pulsed at time any one of the remaining four linesmay be pulsed at time t any one of the remaining three lines may be pulsed at time any one of the remaining two lines may be pulsed at time t,, and the remaining line is pulsed at time Thus, the total number of address permutations for five lines is equal to five times four times three times two times one or 120.

Turning now to FIG. 3, a logic diagram is shown for a central station 11. As previously stated, the central station 11 includes an elevator control 18 which may be of any conventional design and an interface 19 for connecting the elevator control 18 to the lines 13-17. The elevator control 18 is preferably computerized for providing automated control over individual elevator cars in accordance with a predetermined program. The control 18 includes five outputs 20-24 and an enable output 25 for supplying data through the interface 19 to the lines 13-17, respectively. Similarly, data received from the lines 13-17 pass through the interface 19 to five data inputs 26-30 to the elevator control 18. The elevator control 18 has three additional outputs to the interface 19: an output 31 for supplying to the interface 19 an address of a particular remote station to be scanned, an output 32 for shifting or timing the address pulses applied to the lines 13-17 and an output 33 for clearing the interface 19 to release an addressed remote station.

The elevator control 18 provides an address for each remote station 12 to be scanned in the form of five 3-bit binary numbers which are associated with the five lines 13-17 and are arranged in the proper sequence for addressing a desired station. The address from the elevator control 18 is stored in a 3-bit binary address shift register 34. The 3-bit binary numbers are shifted one at a time from the register 34 to a 3-bit to five line decoder 35. The decoder 35 has five outputs 36-40 which are associated with the five lines 13-17, respectively. Depending upon the 3-bit binary number applied from the address shift register 34 to the decoder 35, a signal will appear on one of the five outputs 36-40. The output 36 from the decoder 35 is connected to an SR flipflop 41, which may consist of two OR gates 42 and 43. The set output of the flip-flop 41 is connected through an inverter 44 to the line 13. The output of the flip-flop 41 will be set for applying a pulse or signal over the line 13 when the decoder 35 applies a signal on its output 36. The output 37 from the decoder 35 is connected to the set input of a flip-flop 45 which has an output applied through an inverter 46 to the line 14. Similarly, the output 38 from the decoder 35 is connected to set a flip-flop 47 for applying an output through an inverter 48 to the line 15, the decoder output 39 is applied to set a flip-flop 49 for applying a signal through an inverter 50 to the line 16 and the decoder output 40 is connected to set a flip-flop 51 for applying a signal through an inverter 52 to the line 17. The clear address output 33 from the elevator control 18 is connected through an inverter 53 to simultaneously reset or clear each of the flip-flops 41, 45, 47, 49 and 51 after data transfer with an addressed remote station 12 has been completed, thereby returning each of the lines 13-17 to the normally high logic state.

As indicated above, station 12' has been assigned an address consisting of pulsing the lines 13-17 in the sequence 13, 14, 17, 15 and 16. The station 12' will be addressed by initially storing five 3-bit binary numbers in the address shift register 34 in the sequence corresponding to the lines 13, 14, 17, 15 and 16. As the five 3-bit numbers are shifted from the register 34 to the decoder 35, signals will sequentially appear on the decoder outputs 36, 37, 40, 38 and 39. This will in turn set the flip-flops in the sequence of flipflop 41, flipflop 45, flip-flop 51, flip-flop 47 and finally flip-flop 49. As long as the flip-flop 49 is set after the station 12' has been addressed to maintain the line 16 at a low level, the station 12 will be enabled for data transfer with the elevator control 18 at the central station 11.

After the station 12' is addressed, data can be transferred to or from the station 12 over the lines 13, 14, 15 and 17. The line 13 is connected through an inverter 54 to the elevator control data input 26, the line 14 is connected through an inverter 55 to the data input 27, the line 15 is connected through an inverter 56 to the data input 28, the line 16 is connected through an in verter 57 to the data input 29 and the line 17 is con nected through an inverter 58 to the data input 30. With the exception of line 16 which is required for enabling the addressed station 12' since it is the last line pulsed in addressing the station 12', any or all of the remaining lines 13, 14, 15 and 17 may be used for transferring data from the addressed station 12' through the inverters 54, 55, 56 and 58, respectively, to the elevator control 18. Or, any one of the lines 13, 14, 15 and 17 may be used for transferring data from the elevator control 18 to the addressed station 12. The elevator control 18 is provided with the five data outputs -24 which are connected, respectively, to five NAND gates 59-63. The NAND gates 59-63 are enabled for transferring data from the elevator control 18 by means of the data enable output 25. The outputs of the NAND gates 59-63 are connected to the set inputs of the flipflops 41, 45, 47, 49 and 51, respectively. The elevator control 18 is programmed in a conventional manner to determine for each remote station 12 which of the lines 13-17 will be used for transferring data to the remote station and which of the remaining lines will be used for transferring data from such station.

Details of the remote station 12' are shown in FIG. 4. The remote station 12' comprises an address decoder portion 64 and a data transfer portion 65. The five data lines 13-17 are connected to terminals 66-70 on a terminal strip 71 in the permutation for forming the address of the remote station 12'. For an address consisting of sequentially pulsing the lines l3, 14, 17, I5 and 16, the line 13 is connected to the terminal 66, the line 14 is connected to the terminal 67, the line 17 is connected to the terminal 68, the line 15 is connected to the terminal 69 and the line 16 is connected to the terminal 70. It will be appreciated that the address for the station 12' may be changed merely by changing the permutation in which the lines 13-16 are connected to the terminal strip 71 without making any internal changes in the station 12.

Inputs to the address decoder 64 are provided at the terminals 66-70. The address decoder 64 is identical for all of the remote stations 12. For the address decoder 64 to enable data transfer portion 65, pulses must be applied sequentially to the terminals 66-70 and a pulse or signal then must be maintained on the terminal while data is transferred. Since the five lines 13-17 are normally in a logic high level, inverters 72-76 may be connected to the terminals 66-70 respectively for producing a low logic level for the address decoder 64. The inverters 72-76 are connected to an AND gate 81 to set a latch 82, which consists of two NOR gates 83 and 84. The output of the latch 82 and the output of the AND gate 81 are connected to inputs of a NOR gate 85 which generates an output 86 for clearing the address decoder 64.

The address decoder 64 operates by sequentially setting five flip-flops 87-91 when pulses are sequentially applied to the five terminals 66-70. lf pulses are applied to the terminals 66-70 in any other sequence, the last flip-flop 91 will not be set. The first terminal 66 in the sequence is connected through an inverter 92 to set the flip-flop 87, which is an SR flip-flop consisting of two OR gates 93 and 94. At the same time the flip-flop 87 is set, the signal on the terminal 66 will cause the output of the AND gate 81 to change to remove inputs from the latch 82 and the NOR gate 85. The output of the latch 82 then changes to change the clear output 86 from the gate 85. The clear output 86 previously cleared or reset the flip-flop 87, as well as the other flip-flops 88-91.

The flip-flops 88-91 are of the D type which are set by the simultaneous occurrence of a signal on a D input and a clock pulse. The set or Q output of the flip-flop 87 is conneged to the D input of the flip-flop 88 and the reset or Q output of the flip-flop 87 is connected to a NAND gate 95. The NAND gate 95 has a second input connected to the second terminal 67 in the sequence and an output connected to an inverted OR gate 96. The output of the OR gate 96 is connected to clear the latch 82.

The second terminal 67 is connected to the clock input of the flip-flop 88. If the flip-flop 87 has previously been set so that an input appears on the D terminal of the flip-flop 88, a pulse on the terminal 67 will clock the flip-flop 88 to a set or Q state. The Q output of the flip-flop 88 is connected to the D input of the flip-flop 89, while the Q output and the terminal 68 are connected to a NAND gate 97. After the flip-flop 88 is set, a pulse on the terminal 68 clocks the flip-flop 89 to a set condition to apply a highQ output signal to the D input of the flip-flop 90. The Q output of the flip-flop 89 and the terminal 69 are connected to a NAND gate 98. After the flip-flop 89 is set, a pulse on the terminal 69 sets the flip-flop to apply a signal to the D input of the flip-flop 91. The Q output of the flip-flop 90 and the terminal 70 are connected to a NAND gate 99. Finally, after the flip-flop 90 is set, a pulse on the terminal 70 will set the flip-flop 91.

The NAND gates 97, 98 and 99 are connected to inputs of the OR gate 96, as is the output of the NAND gate 95. In the event of a pulse or signal appearing on either terminal 67 while the flip-flop 87 is cleared, or on the terminal 68 while the flip-flop 88 is cleared, or on the terminal 69 while the flip-flop 89 is cleared, or

on the terminal 70 while the flip-flop 90 is cleared, the OR gate 96 will set the latch 82 to clear all of the flipflops 87-91. This circuitry prevents addressing the station 12 by randomly pulsing the lines 13-17 until the flip-flop 87 is set, continuing to randomly pulse the lines 13-17 until the flip-flop 88 is set, and so forth until the remaining flip-flops 89-91 are set.

The terminal 70 and output of the flip-flop 91 are connected to an AND gate 100 which generates an output 101 for enabling the data transfer portion 65 of the remote station 12'. The AND gate 100 will maintain an enable output 101 as long as the flip-flop 91 has been set and a signal remains on the terminal 70. After data transfer has been completed and the interface 19 at the central station is cleared, all of the terminals 66-70 will go to a high logic level and the AND gate 81, the latch 82 and the NOR gate 85 will again clear the flip-flops 87-91.

The enable output 101 from the address decoder 64 is applied to the data transfer portion 65. For the following description, it will be assumed that the station 12' consists of two elevator call buttons and two related indicator lights located on one floor of a building. At this station, there is a button or switch for calling a down elevator car and a similar button or switch for calling an up elevator car. A down car light and an up car light are associated with the buttons. When a down car is called by pushing the appropriate button, this information is transmitted to the central station over the line 13. The central station 11 confirms this by sending a signal back over the line to illuminate the down light, which may be located within or adjacent the down call button. Similarly, when an up elevator car is requested by pushing the up button, a signal is applied over the line 14 to the central station 11. The central station 1 l confirms this occurrence by applying a signal over the line 17 to cause the up light to become illuminated. Thus, data is transferred from the remote station 12' to the central station 11 over the two lines 13 and 14 and data is transmitted from the central station 11 to the remote station 12' over the two lines 15 and 17. However, it will be appreciated that the data transfer may be over other combinations of the lines. For example, all of the lines 13, 14, 15 and 17 may be used for transferring data either to or from the central station 11 or in any combination thereof. Of course, the line 16 will be used for transferring data with other ones of the stations 12 where a different line is used to enable the addressed station for data transfer.

The enable output 101 from the address decoder portion 64 is applied to inputs of two NAND gates 102 and 103 and to the clock inputs of two D type flip-flops 104 and 105. The down elevator call switch (not shown) is connected to a second input of the NAND gate 102. The output of the NAND gate 102 is connected to the terminal 66 to which the line 13 is connected. The up elevator car call switch (not shown) is connected to a second input of the NAND gate 103. The output of the NAND gate 103 is connected to the terminal 67 to which the line 14 is connected. The terminal 68, to which the line 17 is connected, is connected through an inverter 109 to the D input of the flip-flop 104. When the flip-flop 104 is set, a lamp (not shown) is illuminated by the Q output to indicate that a down car has been called. Finally, the terminal 69, to which the line 15 is connected, is connected through an inverter 111 to the D input of the flip-flop 105. When the flip-flop is set, a lamp (not shown) is illuminated to indicate that an up elevator car has been requested. Thus, the four lines 13, 14, 17 and 15, which are the first four lines in the address for the station 12, may be used for transferring data between the central station 11 and the addressed remote station 12'. It will, of course, be apparent that no data can be transferred over the line 16 when this line is used for maintaining the enable output 101 from the AND gate 100.

As previously indicated, a station may be located on each floor of a building. In addition, a number of stations may be located within an elevator car. For example, each two floor buttons may be grouped together as a station for purposes of transferring data to and from the central station 11 over the lines 13-17. If floors 8 and 9, for example, are grouped together as a station, the gate 102 may be connected to the 8th floor button and the flip-flop 104 may be connected to the 8th floor lamp while the gate 103 is connected to the 9th floor button and the flip-flop 105 is connected to the 9th floor lamp.

Although the present invention has been described above as being embodied in an elevator system, it will be appreciated by those skilled in the art that the invention has numerous other applications. For example, the present invention is readily adaptable to a date processing system in which a centrally located data processor is connected to a large number of peripheral devices, such as remotely located input-output devices. By using only five data lines, the ,data processor may be connected with up to peripheral devices. After a predetermined peripheral device is addressed, four of the five data lines may then be used for transferring data between the addressed peripheral device and the centrally located data processor over four of the lines in a binary coded decimal format. It will be appreciated that when the present invention is used in a data processing system, more than one peripheral device may have the same address. Thus, it is possible for the data processor simultaneously to address and to then supply data to several printers or other output devices at different locations merely by providing the output devices with the same address. Communications may also take place between two remote stations which are simultaneously addressed. In addition, some or all of the peripheral devices may be provided with an interface for addressing other peripheral devices or the data processor. In such a case, the address generating peripheral device will become what has previously been called the central station while the other peripheral devices and the data processor will become the remote stations,

In still another embodiment, the present invention may be adapted for use with devices such as integrated circuit memories wherein limitations in memory size in the past have been primarily due to the number of terminal connections to the memory, as compared to limitations on memory location. In such devices, each memory location within the integrated circuit may be considered as a separate remote station, while the circuitry external to the integrated circuit memory may be considered as the central station. By adopting a permutation addressing system according to the present invention, a large number of memory locations can be addressed over a small number of terminals. Of course, other applications of the present invention will be readily apparent to those skilled in the art.

Although in the preferred form. the address lines are also used as data lines. this is not necessary in the broadest aspects of the invention. Additional lines may be provided for data transfer either alone or in combination with the address lines. Furthermore. each of the lines used for data transfer may transfer data either to or from or both to and from a remote station. It will be appreciated that various other modifications and changes may be made in the above-described invention and in the circuitry for applying the invention without departing from the spirit and the scope of the claimed invention.

What I claim is:

1. A system for transferring information between a central station and up to N factorial other stations over N-conductors comprising, in combination: means connecting all of said stations in parallel to said N- conductors; means at the central station for applying signals sequentially to each of said N-conductors in a predetermined conductor sequence for addressing a preselected one of the other stations and including a shift register for storing in such predetermined sequence indicia of said N-conductors, a decoder having an input connected to receive the conductor indicia from said shift register and having a different output for each different conductor indicia from said shift register, N'flip-flops, means connecting an output from each of said flip-flops to a different one of said N- conductors, means for setting each of said flip-flops in response to a different one of said decoder outputs, and means for sequentially shifting such conductor indicia from said shift register to said decoder whereby said flip-flops are sequentially set to sequentially apply signals on said conductors as the conductor indicia is shifted from said shift register for addressing the preselected station; and address decoder means at each of said other stations responsive only to one predetermined sequence of signals on said N-conductors for selectively enabling such other stations for information transfer with the central station.

2. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 1, wherein at each of said other stations said sequence responsive means includes N second flip-flops, means connecting each of said N-conductors for setting a different one of said N second flip-flops, means assigning a priority to said N second flip-flops corresponding to the predetermined conductor sequence forming the address for such station, said priority means including means for preventing the setting of each flip-flop until the next higher priority flip-flop in the sequence has been set, and means responsive to the setting of the last flip-flop in the sequence for enabling such other station for information transfer.

3. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, wherein said means responsive to the setting of the last flip-flop enables such other station for information transfer over predetermined ones of said N-conductors.

4. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, and including means at each of said other stations for clearing said N second flip-flops at a station when a signal is applied over any of said conductors to a flip-flop and the next higher priority flip-flop in the address sequence for such station has not been set.

5. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, and including means at each of said other stations for clearing said N second flip-flops when a signal is not present on at least one of said N-conductors.

6. A system for transferring information between a central station and'up to N factorial other stations over N-conductors, as set forth in claim 2, wherein said means at each of said other stations responsive to the setting of the last-flip-flop for enabling such other stations for information transfer includes means for enabling such station for information transfer only in response to the simultaneous occurrence of a signal on the last conductor in the address sequence which sets the last flip-flop in the sequence for addressing such other station and of the last flip-flop being set whereby such station is disabled when the signal is removed from such last conductor.

7. A system for transferring information between a central station and up to N factorial other stations over N-conductors comprising, in combination: means connecting all of said stations in parallel to said N- conductors; means at the central station for applying signals sequentially to each of said N-conductors in a predetermined conductor sequence for addressing a preselected one of the other stations; and address decoder means at each of said other stations responsive only to one predetermined sequence of signals on said N-conductors for selectively enabling such other stations for information transfer with the central station, each of said decoder means including N-flip-flops, means connecting each of said N-conductors for setting a different one of said N-flip-flops, means assigning a priority to said N-flip-flops corresponding to the predetermined conductor sequence forming the address for such station, said priority means including means for preventing the setting of each flip-flop until the next higher priority flip-flop in the sequence has been set, and means responsive to setting the last flip-flop in the sequence for enabling such other station for information transfer with the central station.

8. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 7, and including means for clearing said N-flip-flops when a signal is not present on at least one of the conductors. 

1. A system for transferring information between a central station and up to N factorial other stations over N-conductors comprising, in combination: means connecting all of said stations in parallel to said N-conductors; means at the central station for applying signals sequentially to each of said N-conductors in a predetermined conductor sequence for addressing a preselected one of the other stations and including a shift register for storing in such predetermined sequence indicia of said Nconductors, a decoder having an input connected to receive the conductor indicia from said shift register and having a different output for each different conductor indicia from said shift register, N-flip-flops, means connecting an output from each of said flip-flops to a different one of said N-conductors, means for setting each of said flip-flops in response to a different one of said decoder outputs, and means for sequentially shifting such conductor indicia from said shift register to said decoder whereby said flip-flops are sequentially set to sequentially apply signals on said conductors as the conductor indicia is shifted from said shift register for addressing the preselected station; and address decoder means at each of said other stations responsive only to one predetermined sequence of signals on said N-conductors for selectively enabling such other stations for information transfer with the central statiOn.
 2. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 1, wherein at each of said other stations said sequence responsive means includes N second flip-flops, means connecting each of said N-conductors for setting a different one of said N second flip-flops, means assigning a priority to said N second flip-flops corresponding to the predetermined conductor sequence forming the address for such station, said priority means including means for preventing the setting of each flip-flop until the next higher priority flip-flop in the sequence has been set, and means responsive to the setting of the last flip-flop in the sequence for enabling such other station for information transfer.
 3. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, wherein said means responsive to the setting of the last flip-flop enables such other station for information transfer over predetermined ones of said N-conductors.
 4. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, and including means at each of said other stations for clearing said N second flip-flops at a station when a signal is applied over any of said conductors to a flip-flop and the next higher priority flip-flop in the address sequence for such station has not been set.
 5. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, and including means at each of said other stations for clearing said N second flip-flops when a signal is not present on at least one of said N-conductors.
 6. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 2, wherein said means at each of said other stations responsive to the setting of the last flip-flop for enabling such other stations for information transfer includes means for enabling such station for information transfer only in response to the simultaneous occurrence of a signal on the last conductor in the address sequence which sets the last flip-flop in the sequence for addressing such other station and of the last flip-flop being set whereby such station is disabled when the signal is removed from such last conductor.
 7. A system for transferring information between a central station and up to N factorial other stations over N-conductors comprising, in combination: means connecting all of said stations in parallel to said N-conductors; means at the central station for applying signals sequentially to each of said N-conductors in a predetermined conductor sequence for addressing a preselected one of the other stations; and address decoder means at each of said other stations responsive only to one predetermined sequence of signals on said N-conductors for selectively enabling such other stations for information transfer with the central station, each of said decoder means including N-flip-flops, means connecting each of said N-conductors for setting a different one of said N-flip-flops, means assigning a priority to said N-flip-flops corresponding to the predetermined conductor sequence forming the address for such station, said priority means including means for preventing the setting of each flip-flop until the next higher priority flip-flop in the sequence has been set, and means responsive to setting the last flip-flop in the sequence for enabling such other station for information transfer with the central station.
 8. A system for transferring information between a central station and up to N factorial other stations over N-conductors, as set forth in claim 7, and including means for clearing said N-flip-flops when a signal is not present on at least onE of the conductors. 